Memory controller circuits can be used in a variety of computer systems (e.g., desktop personal computers, notebook computers, personal digital assistants, etc.) to facilitate the computer system's processor in accessing memory chips. These memory chips generally include the main memory of the computer system, which typically includes several dynamic random access memory (DRAM) chips. DRAM chips include, for example, synchronous DRAM (SDRAM), extended data out (EDO) DRAM, Rambus (R)DRAM, DDR (double data rate) and DRAM chips. The memory controller typically includes a memory interface for communicating with one or more of such DRAM chips via a memory bus. The memory controller includes buffers to drive signals onto the memory bus. In addition, the memory controller typically includes a system interface to communicate with system processor(s) via a system bus. The memory controller uses these interfaces to route data between the processor and the DRAM chips using appropriate address, control and data signals.
In some systems, the memory bus is terminated with resistors to a mid-range voltage. As a result, if the output buffers are enabled (i.e., pulling up or pulling down the voltage of the memory bus lines) during idle periods, the buffers dissipate power during the idle periods. This power dissipation is undesirable in many applications.
One method of reducing power dissipation by the buffers during idle periods is to implement the buffers as three-state buffers that present a high impedance to the memory bus when disabled. Once the idle period ends, the buffers are enabled, allowing them to drive signals onto the memory bus. However, driving the voltage levels of the memory bus lines takes a finite amount of time. Thus, such systems typically have a time period between when the buffers are enabled and when the signals on the memory bus are at valid logic levels. This “buffer enable” delay if large enough can undesirably increase latency in accessing the memory in some memory designs.